MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202611007909 A) filed by Indian Institute Of Technology, Jammu on January 27, 2026, for Low-Overhead Secure Memory Scrambling System And Method Using Generic Lfsr.
Inventors include Kumar, Gaurav; and Ahlawat, Satyadev.
The application for the patent was published on July 10, 2026, under issue no. 28/2026.
Abstract: The present disclosure provides a lightweight, and secure memory scrambling system (100) and method (200) based on a generic linear feedback shift register (LFSR) designed to enhance the security of DDR3 main memory against cold boot and related side- channel attacks. The proposed mechanism introduces an address- and seed-dependent dynamic LFSR configuration that eliminates differential keystream periodicity, thereby preventing stencil-based key recovery and significantly increasing resistance to differential analysis. Unlike conventional AES-based memory encryption solutions that impose substantial latency and hardware overhead, the disclosed system (100) delivers comparable security assurances while maintaining low hardware complexity and zero access latency. FPGA implementation on the Xilinx VCU118 platform demonstrates that the system (100) requires only 252 LUTs, 256 registers, and 104 slices, matching the footprint of the Intel DDR3 scrambler, yet provides superior robustness against cold boot, warm boot, probing, and bus-level attacks.
Disclaimer: Curated by HT Syndication.
