MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202611082690 A) filed by Indian Institute Of Technology, Mandi on July 05, 2026, for Low-Dropout Voltage Regulator With Four-Quadrant Discrete-Time Parametric Demodulator.
Inventors include Amit Kumar; and Dr. Hitesh Shrimali.
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: A low-dropout voltage regulator architecture is disclosed for precision analog power management applications. Conventional low-dropout regulators often require external capacitors for stability and suffer from residual noise when using conventional chopper stabilisation techniques due to thermal noise aliasing in CMOS switch demodulators. The regulator comprises an error amplifier (303) with a cross-coupled transconductance-enhanced differential pair, an active frequency compensation network (302) based on a parasitic voltage-controlled current source, and a chopper-stabilised signal path. The demodulator stage (501) includes a double complementary discrete-time parametric amplifier (1001) arranged in a four-quadrant configuration. The parametric amplifier performs amplification through charge redistribution between capacitors without a transistor channel conducting during the amplification phase. Dual parametric amplifier paths (501-1, 501-2) operating on complementary clock phases and a buffer (501-3) enable continuous demodulation. The architecture achieves high loop stability without external capacitors and improved noise performance through structural cancellation of flicker noise and even-order distortion.
Disclaimer: Curated by HT Syndication.
