MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202641093610 A) filed by Vidyavardhaka College Of Engineering on August 03, 2026, for Localized Micro Rollback Memory Pipeline For Radiation-Hardened Edge Processors.
Inventors include Prof. Harshitha K; Dr. Nagaraja B G; Dr. Chandrashekar M Patil; Prof. Jaswanth. V; Nihal G Deshakulkarni; Nimish Vihan; and Prof. Meghana S.
The application for the patent was published on August 07, 2026, under issue no. 32/2026.
Abstract: Developing computers capable of operating in such harsh conditions, for instance, in the Large Hadron Collider (LHC) or in outer space, is a challenging task. In these places, processors need to handle a large amount of data very quickly while dealing with large amounts of radiation or collisions. Sometimes high-energy particles hit the chip, causing data to crash in memory. This is called a single-event upset (SEU), which can lead to the loss of important data. Engineers typically address this issue by designing the same processor three times over for increased precision, in a method known as triple modular redundancy (TMR). While this method is safe, it uses a lot of extra space and power, which is not suitable for smaller systems with limited energy. In this work, we introduce a simple and most efficient solution called “Localized Micro rollback”. Instead of replicating the entire processor, it focuses only on the section where the error occurs. When an error is detected, it pauses the execution for just 1 clock cycle and fixes the problem immediately. We tested our design using Cadence Genus simulations at 45nm technology and also implemented it on an Arty A7-100T FPGA board. The results show that our system can find and fix the error without affecting the real-time performance. Overall, our design is a strong and efficient way to handle radiation errors with very little extra hardware (less than 2%), making it a practical choice for future systems that work in harsh conditions.
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