MUMBAI, India, June 26 -- Intellectual Property India has published a patent application (202641072897 A) filed by Koneru Lakshmaiah Education Foundation on June 12, 2026, for Integrating Scan Pulse Modules For Enhanced Clock Generation Test Coverage.
Inventors include Mr. Annavarapu Praneeth; Dr. Govardhani Immadi; Dr. Prabhakar V. S. V; and Dr. Venkata Narayana Madhavareddy.
The application for the patent was published on June 19, 2026, under issue no. 25/2026.
Abstract: The present invention discloses the development of ass more and more people want communication systems to work together without complications, interoperability between UART and SPI has become an important challenge in embedded systems. While UART provides reliable asynchronous communication, SPI is faster and does so synchronously. To bridge the two divergent systems involves a sophisticated hardware approach to achieve the lowest possible latency and resource utilization. In this work, the author describes a Register-Transfer Level (RTL) design of a high-performance, FIFO-less UART–to–SPI communication bridge built using Finite State Machines (FSMs). The design is built around a modular dual-FSM architecture, where one is dedicated to receiving over UART and the other is focused on transmitting over SPI. While the UART FSM is in charge of bit sampling, serial-to-parallel conversion, and parity checking, the SPI FSM is responsible for clock control, parallel- to-serial conversion, and data transfer synchronization. Conventional FIFO buffering has been substituted for a direct handshake approach between the FSMs. With this, latency is lowered, hardware is minimized, and throughput is maximized, all at the same time. With regard to the bridge design, it is fully synthesizable in Verilog HDL. It has been tested in ModelSim and simulations in Xilinx Vivado to verify the timing, synchronization, and integrity of the data and communication protocols. The bridge’s neat architecture and scalability, in the communication systems make it ideal for embedding as a customization. FIG.1
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