MUMBAI, India, July 31 -- Intellectual Property India has published a patent application (202647088782 A) filed by Qualcomm Incorporated on July 21, 2026, for Integrated Circuits (ics) Having Separate Signal And Power Distribution Network (pdn) Interconnect Structures For Reduced Power Signal Routing Congestion And Path Lengths, And Related Three- Dimensional (3d) Ics (3dics) And Fabrication Methods.
Inventors include Li, Yue; Sun, Yangyang; Popovic, Darko; and Lisk, Durodami.
The application for the patent was published on July 24, 2026, under issue no. 30/2026.
Abstract: Integrated circuits (ICs) having a separate signal and power distribution network (PDN) interconnect structures for reduced power signal routing congestion and path lengths, and related three-dimensional (3D) ICs (3DICs) and fabrication methods. The IC includes a separate signal interconnect structure providing input/output (I/O) signal routing, and a PDN interconnect structure for providing power distribution signal routing. The signal interconnect structure is disposed on a first side of a semiconductor layer in the IC, and the PDN interconnect structure is disposed on a second side of the semiconductor layer opposite of the first side. In this manner, performance of semiconductor devices in the semiconductor layer can be improved, because power distribution signals do not have to be routed in a shared interconnect structure that is also used for routing I/O signals, which could otherwise congest and increase power distribution signal routing path lengths in the IC.
Disclaimer: Curated by HT Syndication.
