MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202641058105 A) filed by The Principal, Mepco Schlenk Engineering College on May 07, 2026, for Implementation Of Position Variant Radial Stick Cipher (pvrsc) For Resourcw Constrained Iot Devices.
Inventors include Dr. W. Sylvia Lilly Jebarani; Dr. N. Sivasankari; Dr. V. Jeyalakshmi; Mr. S. Nishmanul Hag; and Mr. M. Shah Muhammed Ilyas.
The application for the patent was published on July 03, 2026, under issue no. 27/2026.
Abstract: ABSTRACT OF THE INVENTION Implementation of Position-Variant Radial Stick Cipher (PVRSC) for ResourceConstrained loT Devices The Position-Variant Radial Stick Cipher (PVRSC) is a method for encoding plaintext characters into unique visual symbols designed for secure communication on devices with limited resources. Each character is transformed into a symbol characterized by three parameters: stroke angle, stroke count, and dot modifier, creating a large set of possible encodings. A session-specific seed, based on device uptime, introduces time-based variability. The system computes a 32-bit intermediate value by combining the character's ASCII code, its position in the message, and the session seed through bitwise operations. This value is then processed with an avalanche mixing '.function inspired by the MurmurHash3 finaliser to maximize diffusion and sensitivity to input changes. The resulting hash output is used to generate the symbol's visual parameters-angular orientation, number of radial strokes, and dot placement. Symbols are drawn on a circular coordinate system and displayed on an SSD1306 OLED screen using trigonometric calculations, ensuring clear differentiation and efficient use of space. Symbols are arranged in sequence with spacing optimized for low-resolution displays. This implementation is tailored for embedded platforms like the ESP32, emphasizing low memory use and computational efficiency. Overall, PVRSC offers a lightweight, visually obfuscated encoding suitable for loT applications, balancing complexity, rendering speed, and hardware constraints
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