MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641074123 A) filed by Robert Kingsly A on June 15, 2026, for Hybrid Tensor-Graph Processing Architecture With Unified Sparse-Aware And Pod-Scalable Memory/Fabric.
Inventor includes Robert Kingsly A.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: A programmable accelerator architecture is disclosed that combines a dense tensor array engine and a sparse graph traversal engine under a unified instruction and memory system. The architecture employs a unified operand store with activation, weight, and sparse-mask regions; mode-selectable arithmetic execution across INT8, BF16, FP8 (E4M3/E5M2), and FP4; instruction-triggered HBM burst streaming with remapped operand injection; and a fabric arbitration path that supports dual-engine output convergence and pod-scale interconnect accounting. The disclosed microarchitecture enables efficient workload switching between dense and sparse computation, high-throughput graph frontier processing, and scalable multi-chip deployment while preserving a compact control plane.
Disclaimer: Curated by HT Syndication.
