MUMBAI, India, Sept. 14 -- Intellectual Property India has published a patent application (202641108053 A) filed by Sathyabama Institute Of Science And Technology on September 08, 2026, for Hybrid Logic-Based Twisted Ring Counter For Area And Power Optimization.
Inventors include A. Anjaline Jayapraba; Vasundra R; and Barani V.
The application for the patent was published on September 11, 2026, under issue no. 37/2026.
Abstract: In modern digital systems, high-speed and low-power arithmetic circuits are essential for improving the performance of processors, digital signal processing systems, communication systems, and VLSI applications. Binary addition is one of the basic arithmetic operations, and the speed of an adder directly affects the overall system performance. Conventional Ripple Carry Adders suffer from carry propagation delay because the carry generated at one stage must pass through the following stages. To overcome this limitation, the proposed work focuses on the design and implementation of an efficient Ladner-Fischer parallel-prefix adder for high-speed binary addition. The proposed architecture uses a tree-based parallel-prefix structure to generate carry signals efficiently and simultaneously. It consists of pre-processing, carry generation, and post-processing stages. The input bits are used to generate propagate and generate signals, which are processed using black cells and gray cells to obtain the required carry signals. The generated carries are then combined with the propagate signals to produce the final sum. This parallel carry generation reduces the critical carry propagation delay and improves the speed of addition. The proposed architecture also focuses on reducing hardware area and power consumption by optimizing the gate-level structure and minimizing unnecessary logic and switching activity. The design can be implemented using Verilog HDL, with Xilinx tools for FPGA synthesis and implementation and ModelSim for simulation and verification. The proposed Ladner-Fischer adder is suitable for microprocessors, DSP systems, FPGA-based systems, VLSI circuits, and communication applications, providing an efficient solution for high-speed and low-power binary arithmetic operations.
Disclaimer: Curated by HT Syndication.
