MUMBAI, India, Aug. 17 -- Intellectual Property India has published a patent application (202641096319 A) filed by Velammal Engineering College on August 10, 2026, for Hybrid Logic-Based Twisted Ring Counter For Area And Power Optimization.
Inventors include Dr. Leena Jasmine; Dr. Manju. S; Dr. K. Thilagam; Mrs. Nandhini. M; Dr. Sumathi. S; Dr. N. Deepa; Mrs. Kavitha. S; Mrs. Sarupriya. S; and Mrs. Dolly Irene. J.
The application for the patent was published on August 14, 2026, under issue no. 33/2026.
Abstract: The present invention relates to the field of digital electronics and Very Large-Scale Integration (VLSI) design, and more particularly to a hybrid logic-based twisted ring counter for achieving area and power optimization. The proposed counter comprises a plurality of edge-triggered D flip-flops connected in a twisted ring configuration, a hybrid logic block, a feedback path, a clock input, and a reset circuit. The hybrid logic block processes the complemented output of the final flip-flop and generates an optimized feedback signal for the first flip-flop, thereby reducing transistor count, switching activity, propagation delay, and overall power consumption while maintaining reliable sequential counting operation. The proposed architecture generates 2n valid states for an n-stage twisted ring counter and provides improved silicon area utilization and Power-Delay Product (PDP) compared with conventional twisted ring counter implementations. The invention is suitable for implementation using CMOS, FPGA, ASIC, and System-on-Chip (SoC) technologies and is applicable to digital communication systems, timing and control circuits, frequency dividers, finite state machines, memory addressing circuits, Internet of Things (IoT) devices, and other low-power embedded applications requiring compact, high-speed, and energy-efficient digital counter architectures.
Disclaimer: Curated by HT Syndication.
