MUMBAI, India, Nov. 2 -- Intellectual Property India has published a patent application (202641125379 A) filed by Madhankumar C; Ms Madhumitha D - Rathinam Technical Campus; Mr Logesh S - Rathinam Technical Campus; Ms Priyadharshini T - Rathinam Technical Campus; and Mr Mahesh L. A. - Rathinam Technical Campus on October 21, 2026, for Highly Efficient Three-Operand Adder Leveraging Weinbergerprefixarchitectureforsecuritysystems.
Inventors include Ms Madhumitha D - Rathinam Technical Campus; Mr Logesh S - Rathinam Technical Campus; Ms Priyadharshini T - Rathinam Technical Campus; and Mr Mahesh L. A. - Rathinam Technical Campus.
The application for the patent was published on October 30, 2026, under issue no. 44/2026.
Abstract: ABSTRACT The present invention relates to a high-speed and energy-efficient three-operand binary addition architecture based on a Weinberger prefix architecture for VLSI, FPGA, digital signal processing, and security-oriented computing systems. Addition is a fundamental arithmetic operation in modern digital systems, and the performance, power consumption, hardware area, and propagation delay of an adder directly influence the efficiency of larger computational architectures. Conventional ripple-carry and carry-lookahead based addition structures may introduce trade-offs between carry propagation delay, hardware resource utilization, switching activity, and power consumption. The proposed architecture addresses these limitations by integrating recursive Weinberger carry computation with a three-operand parallel addition mechanism and a selective approximation technique for lower-order bits. The proposed system comprises a 16-bit three-operand Weinberger adder configured to simultaneously process three input operands A, B, and C. The architecture employs recursive generation and propagation of carry information to reduce the delay associated with sequential carry computation. Bitwise propagation, bitwise generation, and group generation signals are utilized to construct the carry computation structure, thereby enabling parallel processing of carry information across multiple bit positions. A double-bit conditional addition mechanism is incorporated to pre-compute possible sum outputs corresponding to different carry input conditions and to select the appropriate result according to the actual carry. This arrangement reduces the dependency of subsequent computations on sequential carry propagation and provides an architecture suitable for high-speed arithmetic processing. The Weinberger recurrence further permits the generation and propagation signals to be organized into different group sizes, enabling scalability of the addition structure for different operand widths and computational requirements. To further improve the trade-off between computational accuracy, power consumption, hardware complexity, and latency, the proposed system incorporates a hybrid approximate-exact computation structure. The 16- bit three-operand architecture is divided into a lower eight-bit Least Significant Bit (LSB) estimation block and an upper eight-bit Most Significant Bit (MSB) precise computation block. The LSB block employs simplified carry-generation and propagation logic to reduce the number of active hardware elements, switching activity, and computational latency. Since the lower-order bits generally have a smaller contribution to the overall numerical significance of the output, approximation is selectively applied to this portion of the architecture. The LSB block produces a partial sum and an intermediate carry, referred to as Carrymid, which is subsequently supplied to the upper computation stage. In contrast, the MSB block maintains accurate computation using two-bit conditional sum modules and the Weinberger recursion structure, thereby preserving the accuracy of the higher-order output bits. The resulting hybrid architecture combines approximate low-order computation with precise high-order computation to obtain a balance between energy efficiency, speed, hardware utilization, and computational accuracy. The proposed architecture is implemented and evaluated using a digital hardware design and synthesis environment. The design is represented at the Register Transfer Level and subjected to synthesis to generate a gate-level implementation using standard-cell or FPGA-oriented resources. The evaluation considers multiple arithmetic architectures, including Ripple-Carry Adder (RCA), Carry- Lookahead Adder (CLA), conventional Weinberger adder, and Approximate Weinberger adder. The comparative analysis considers switching power, logic resource utilization, latency related characteristics, and area requirements. The reported implementation results indicate that the conventional Weinberger architecture provides high-speed parallel carry computation at the cost of increased hardware resources and switching activity, while the approximate Weinberger architecture reduces resource utilization and switching activity by simplifying the lower-order computation. In the reported FPGA resource comparison, the conventional Weinberger implementation uses 38 LUTs and 16 slices, whereas the approximate Weinberger implementation uses 27 LUTs and 9 slices, demonstrating the hardware savings obtained through selective approximation. The proposed three-operand addition architecture is further configured for use in security and cryptographic processing. In the demonstrated encryption framework, three input operands comprising a plaintext representation, a secret key, and a noise or nonce vector are simultaneously processed by the three-operand adder. The parallel addition operation produces a corresponding encrypted output through modular arithmetic, thereby reducing the need for multiple sequential addition stages. The use of Weinberger recursive carry computation provides parallel carry processing for the arithmetic operation, while the approximate lower-bit computation provides a mechanism for reducing hardware complexity and energy consumption in applications where limited numerical approximation can be tolerated. In the reported demonstration, the plaintext message “HELLO” is represented using ASCII values and combined with key and nonce values, producing a hexadecimal encrypted output of A0 A5 CA A7 E4. The architecture is therefore applicable to lightweight cryptographic processing where arithmetic throughput, hardware efficiency, and energy consumption are important design considerations. Accordingly, the proposed invention provides a hybrid three-operand Weinberger prefix addition architecture that combines recursive parallel carry generation, double-bit conditional addition, selective lower-bit approximation, and precise higher-bit computation within a single arithmetic framework. The architecture provides a configurable trade-off between speed, power, area, and computational accuracy and can be employed in high-performance VLSI systems, FPGA-based accelerators, digital signal processing units, image and video processing systems, embedded computing platforms, machine-learning-oriented hardware, Internet-of-Things devices, and lightweight security and cryptographic systems. The proposed architecture thereby provides an efficient arithmetic processing mechanism for applications requiring simultaneous multi-operand addition with reduced latency and hardware overhead while maintaining higher-order computational accuracy.
Disclaimer: Curated by HT Syndication.
