MUMBAI, India, Aug. 24 -- Intellectual Property India has published a patent application (202641097764 A) filed by Easwari Engineering College; and Srm Institute Of Science And Technology,ramapuram Campus on August 13, 2026, for High Speed Median Filter Architecture Using Optimized Sorting For Image Denoising.
Inventors include Bhuvanesh G; Goushik M; Gowtham C; and Senthamizh Selvi R.
The application for the patent was published on August 21, 2026, under issue no. 34/2026.
Abstract: Impulse (salt-and-pepper) noise severely degrades image quality by introducing extreme pixel values. To address the high computational complexity of median filtering in large sliding windows, this work presents a hardware-optimized 5×5 median filter implemented on FPGA using an FSM-controlled Odd–Even Bubble Sort algorithm. The architecture focuses on reduced combinational depth through adjacent compare–exchange operations, making it more FPGA-efficient than conventional sorting networks. Stage-level pipelining is applied to minimize critical path delay and increase operating frequency, while a 2-lane SIMD architecture enables parallel processing of sliding windows, achieving nearly 50% faster reconstruction than a single-lane design. PSNR and MSE evaluations confirm strong denoising performance across varying noise densities, demonstrating an efficient and scalable real-time FPGA solution.
Disclaimer: Curated by HT Syndication.
