MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641073747 A) filed by Robert Kingsly A on June 14, 2026, for High Performance Vector-Enhanced Risc-V Processor Architecture For Scientific & Ai Computing.
Inventor includes Robert Kingsly A.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: This comprehensive high performance design is a 64-bit, four-thread SMT RISC-V core implementing RV64IMAFD, Zicsr, Zifencei, RVV, and a custom AI data path. The microarchitecture combines a 16-wide fetch front end, 12-wide decode, 16-wide dispatch and retire, a 1536-entry ROB, per-thread rename and checkpoint recovery, a class-partitioned reservation-station fabric, a hybrid branch predictor, and a private/shared cache hierarchy culminating in L2 and L3 memory levels. Vector execution is lane-based and SEW-polymorphic, and vector memory activity is sequenced through the LSU. The design also includes M-mode CSR/trap control, redirect handling, privilege checks, and counter reporting suitable for system software and diagnostics.
Disclaimer: Curated by HT Syndication.
