MUMBAI, India, Sept. 22 -- Intellectual Property India has published a patent application (202631093330 A) filed by National Institute Of Technology Mizoram on July 31, 2026, for High-Performance Cylindrical Gate-All-Around Nano-Field-Effect Transistor System For Rapid Carrier Switching And Its Fabrication Process Thereof.
Inventors include Prof. Dr. Rudra Sankar Dhar; Dr. Rasmita Barik; Dr. Swagat Nanda; and Dr. Potaraju Yugender.
The application for the patent was published on September 18, 2026, under issue no. 38/2026.
Abstract: The cylindrical gate-all-around nano-field-effect transistor system and fabrication method are disclosed for rapid carrier switching. The system features a substrate (102) and a cylindrical core-shell nanowire channel (104) extending axially between a source region (106) and a drain region (108). The channel comprises a cylindrical inner core region (104A) of strained silicon-germanium and an outer shell layer (104B) of strained silicon epitaxially disposed over the core to define a Type-II heterostructure quantum-well interface. A gate dielectric stack (110), comprising a silicon dioxide interfacial layer (110A) and a coaxially surrounding hafnium oxide (HfO_2) high-k dielectric layer (110B), is positioned around the outer shell. A gate electrode (112) sits over a central portion of the channel, flanked by a pair of high-k dielectric corner spacers (114) enclosing gate underlap regions. The spacers focus electric field lines in the underlap regions to enhance carrier confinement, promote ballistic transport, and suppress subthreshold short-channel leakage.
Disclaimer: Curated by HT Syndication.
