MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202647113562 A) filed by Tenstorrent Usa, Inc. on September 22, 2026, for Hardware Managed Synchronization Of Coprocessor Instruction Execution.
Inventors include Gilani, Syed; and Merlini, Marco.
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: Systems and methods related to hardware managed synchronization of coprocessor instruction execution are disclosed herein. A system may include a processor configured to generate instructions and a coprocessor configured to perform operations for the instructions. The system may also include instruction-handling circuitry within the transmission paths between the processor and the coprocessor, stall circuitry located between instruction-handling circuitry and the coprocessor, and synchronization circuitry. The synchronization circuitry may monitor the instruction-handling circuitry and may control the stall circuitry. The synchronization circuitry may be configured to selectively delay delivery of instructions at the stall circuitry based on monitoring the instruction-handling circuitry.
Disclaimer: Curated by HT Syndication.
