MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202611071308 A) filed by Noida Institute Of Engineering And Technology Niet on June 08, 2026, for Hardware-Enforced Curriculum-Based Fleet Routing System With Heterogeneous Graph Attention Accelerator For Electric Vehicle Logistics.
Inventors include Dr. Ghazala Sultan; and Al Yusra Sikander.
The application for the patent was published on August 07, 2026, under issue no. 32/2026.
Abstract: A hardware-enforced curriculum-based fleet routing system for electric vehicle logistics optimization comprises a curriculum controller circuit (100) with a phase state register bank (110) having write-lock latches (112) that sequentially activate constraint enforcement circuits across three training phases progressing from topological capacity constraints through battery energy constraints to time window constraints. A heterogeneous graph attention accelerator (200) employs type-specific projection parameter banks (210) in dedicated block random access memory regions (212) for depot, customer, and charging station nodes, with an input-output memory management unit (230) enforcing access isolation. An interconnect firewall controller (420) with a bus transaction filter (422) enforces memory isolation between a policy parameter storage region (400) and an environment simulation region (410). A hardware multiplexer (314) selects phase-specific hyperparameters from read- only configuration memory (312) for a proximal policy optimization pipeline (300), while a secure element (430) maintains monotonic counter-based attestation.
Disclaimer: Curated by HT Syndication.
