MUMBAI, India, Sept. 22 -- Intellectual Property India has published a patent application (202641110295 A) filed by Vellore Institute Of Technology on September 14, 2026, for Hardware-Aware Prompt Tensor Compiler And Executable Binary Packet Pipeline For Deterministic On Device Neural Execution.
Inventors include Ramesh Kumar D; and M S Shabreena.
The application for the patent was published on September 18, 2026, under issue no. 38/2026.
Abstract: The present invention relates to a Hardware-Aware Prompt Tensor Compiler and Executable Binary Packet Pipeline for deterministic on-device neural execution. The system receives a natural-language command and processes the command through a deterministic Rule-Table Dependency Mapping Unit and Finite-State Reduction Engine to extract execution-relevant intent without neural preprocessing or conventional software tokenization. A Deterministic Projection Adapter (DPA) maps extracted canonical vectors into a latent feature space compatible with a pretrained edge Large Language Model (LLM). The resulting feature vectors, dependency information, and hardware control parameters are compiled into a Deterministic Prompt Tensor Object (DPTO) comprising a fixed control header, node vector matrix, and adjacency edge matrix. A Direct Memory Access (DMA) controller transfers the DPTO directly into NPU scratchpad SRAM or VTCM, bypassing intermediate system DRAM transfers. The NPU directly processes the pre-aligned vectors through SIMD projection layers for Key-Value attention initialization. The invention reduces tokenization overhead, memory traffic, preprocessing latency, Time-To-First-Token (TTFT), and energy consumption for resource-constrained edge AI platforms.
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