MUMBAI, India, Sept. 7 -- Intellectual Property India has published a patent application (202621087975 A) filed by Suyash Verma; and Rajveer Singh Rajput on July 18, 2026, for Hardware Acceleration System For Lattice-Based Post-Quantum Cryptography And Method Thereof.
Inventors include Suyash Verma; and Rajveer Singh Rajput.
The application for the patent was published on September 04, 2026, under issue no. 36/2026.
Abstract: A post-quantum cryptographic hardware apparatus (100) includes a hardwired on-chip control state machine (110) driving a physical multiplexer control line. An arithmetic execution core (120) includes a multiplexer-switched dual-reduction logic circuit (122) with a shared physical multiplier array (124) routing data to a first physical electrical routing path (126) having low-bit-width register lanes with hardwired Barrett reduction logic gates, or a second physical electrical routing path (128) having high-bit-width register lanes with a pipelined Montgomery reduction tree. A collision-free multi-banked SRAM array (130) provides concurrent parallel access to coefficient operands. A hardwired address generation unit (140) interleaves coefficient addresses using a physical bit-reversal wiring network. A physical masking engine (150) uses an on-chip true random number generator (152) to split secret data into shares processed on geographically parallel layout tracks (154, 156) driven by a shared physical power distribution ring (158) at substantially coincident clock edges to uniformize instantaneous current draw.
Disclaimer: Curated by HT Syndication.
