MUMBAI, India, July 24 -- Intellectual Property India has published a patent application (202611065751 A) filed by Noida Institute Of Engineering And Technology Niet on May 25, 2026, for Hardware-Accelerated Graph Neural Network System For Exact Algorithmic Execution Via Ensemble Perceptron Architecture.
Inventors include Vikash Tripathi; and Dr. Anand Kumar Gupta.
The application for the patent was published on July 17, 2026, under issue no. 29/2026.
Abstract: A hardware-accelerated graph neural network processing system (100) for exact execution of distributed graph algorithms on attributed graphs addresses approximation errors in conventional neural algorithmic reasoning systems. The system (100) comprises an input encoding module (101) applying blockwise orthogonal encoding to binary node features, an ensemble perceptron processing unit (102) with independently trained multi-layer perceptron instances (103) averaged by ensemble averaging logic (108), a binarization module (104) applying Heaviside step function conversion to exact binary, a dual-mask projection unit (105) separating computation-local and communication-message features through complementary binary projection matrices, and a message aggregation unit (106) performing neighbour summation on communication-message features. The interaction between ensemble averaging and Heaviside binarization achieves zero-error binary output across iterative rounds. The system executes message flooding, breadth-first search, depth-first search, and Bellman-Ford algorithms with exact precision on bounded-degree graphs for network routing hardware and distributed computing accelerator platforms.
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