MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202611071631 A) filed by Noida Institute Of Engineering And Technology Niet on June 09, 2026, for Hardware-Accelerated Graph Attention Network System With Edge-Aware Embedding For Time- Constrained Vehicle Routing Optimization.
Inventors include Sanjay Kumar Nayak; and Km Prashansa Singh Yadav.
The application for the patent was published on August 07, 2026, under issue no. 32/2026.
Abstract: A hardware-accelerated vehicle routing optimization system (100) for solving time-constrained vehicle routing problems on directed transportation networks comprises a routing network state interface (110) receiving node feature matrices, sparse adjacency matrices, and normalized edge feature vectors, a vehicle state register file (120) storing current location, active customer bitmap, and remaining time horizon, a graph attention network accelerator (130) computing edge-induced attention scores by fusing attention coefficients with edge feature values before softmax normalization to generate node embedding vectors, a cross-attention unit (140) generating a global graph embedding vector from vehicle state queries and node embeddings, a policy inference unit (150) computing routing decisions, a masking controller (160) enforcing temporal and visit constraints through a latched binary mask, and a commit-lock finite state machine (170) generating a one-time latch signal write-locking configuration registers after initialization to establish an immutable hardware boundary during routing operation.
Disclaimer: Curated by HT Syndication.
