MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202641112689 A) filed by G. Pullaiah College Of Engineering And Technology on September 20, 2026, for Gnrfet Based Ternary Half Adder And Multiplier.
Inventors include T. Kishore; Dr. P. Venkatramana; Dr. V. Vijaya Kishore; M. Kiranmayee; Dr. Pasuluri Bindu Swetha; T. Deepa; R. Deepthi Crestose Rebekah; P. Raga Chandrika; A. Sreepradha; and Dr. S. Javid Basha.
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: The detailed design of ternary logic schematics is proposed in this study. The ternary logics offer fast computations, reduced chip size and reduced interconnect complexity compared to conventional binary logics. Hence, ternary logic allows lower complex, high performance and power efficient schematics for the future integrated circuits (ICs). A novel methodology is proposed in this work to develop ternary schematics with the graphene nanoribbon field effect transistors (GNRFETs). The complicated schematics like adder and multiplier are designed in this paper. These schematics are designed using the 3:1 multiplexer to improve the performance. The proposed schematics are simulated in HSPICE for functional verification and performance analysis. The various performances including delay, power and power delay product (PDP) are investigated for proposed schematics. Furthermore, performance of the proposed GNRFET designs are compared with carbon nanotube FET (CNTFET) designs. It is investigated that proposed designs shows the enhanced performance up to 53.18% over the conventional CNTFET based designs.
Disclaimer: Curated by HT Syndication.
