MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641076286 A) filed by Vellore Institute Of Technology on June 19, 2026, for Geometry-Aware Wafer Defect Classification System With Incremental Model Adaptation And Method Of Operation.
Inventors include Aju D; Jay Krishna Kamlekar; Manas Maahir. R; and Poojana Boina Kartheek Yadav.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: The present disclosure proposes a geometry-aware wafer defect classification system (100) that processes wafer map data using polar-coordinate representation, convolutional neural network-based feature extraction, transformer-based global feature learning, and incremental model adaptation for improved defect recognition and retention of previously learned classification knowledge in semiconductor manufacturing environments. The system (100) comprises a computing device (102) having a processor (104) and a memory (106) storing one or more instructions executable by the processor (104). The processor (104) is configured to execute plurality of modules (108) for performing dataset management, pre-processing, feature extraction, feature adaptation, defect classification, continual learning, training optimization, and visualization operations. The wafer defect classification system (100) is suitable for deployment in semiconductor manufacturing, inspection, yield- management, and process-monitoring environments. The wafer defect classification system (100) capable of generating probability-based defect classification outputs for multiple predefined defect categories.
Disclaimer: Curated by HT Syndication.
