MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641075432 A) filed by Vellore Institute Of Technology on June 18, 2026, for Fpga-Based Hardware Accelerator For Seismic Event Classification.
Inventors include Aarthy M; Gokulapriya S; Shah Mukt Bhavin; and R Balavasanth.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: ABSTRACT FPGA-BASED HARDWARE ACCELERATOR FOR SEISMIC EVENT CLASSIFICATION A hardware accelerator for seismic event classification comprises a programmable logic device (110) performing neural network inference using fixed-point arithmetic, on-chip memory blocks (140) storing quantized neural network parameters including INT8 weights, INT32 biases, scale factors, and zero-point values, and cascaded neural network layers (120) receiving input features representing seismic signal characteristics and processing the input features through sequential layers. Each layer comprises a multiply accumulate unit (122) performing signed multiplication of input features with weights from the on-chip memory blocks (140) and accumulating products with bias values, and a requantization module (124) converting accumulated output from higher bit-width format to INT8 format using integer multiplication by a scale factor and arithmetic right-shift. A comparator (130) coupled to a final layer compares final layer output against a threshold value to produce a classification output indicating whether input features correspond to a seismic event or noise. (Fig. 1)
Disclaimer: Curated by HT Syndication.
