MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641075538 A) filed by Vardhaman College Of Engineering on June 18, 2026, for Fpga Accelerator System Featuring Adaptive Compute Blocks For Training Deep Neural Networks.
Inventors include Mr. R. Phani Vidyadhar; Mr. Nagarjuna Malladhi; Mrs. A. Geethanjali; Mr. Tareeq Zaid; Dr. I. Babu; and Dr. B. Srikanth.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: FPGA accelerator system featuring adaptive compute blocks for training deep neural networks is the proposed invention. The advanced FPGA accelerator system introduces an innovative adaptive compute block framework for comprehensive deep neural network training that integrates computational optimization protocols with dynamic resource allocation mechanisms, facilitating real-time training acceleration, adaptive computation optimization, and robust performance validation while maintaining seamless AI development integration and operational efficiency for consistent neural network applications. The comprehensive FPGA framework employs adaptive computational algorithms and intuitive processing protocols, utilizing embedded parallel processing arrays and energy-efficient calculation systems to ensure timely gradient computation, enhanced neural network understanding, and optimal training reliability while maintaining continuous performance monitoring capabilities.
Disclaimer: Curated by HT Syndication.
