MUMBAI, India, Sept. 14 -- Intellectual Property India has published a patent application (202641107218 A) filed by Mlr Institute Of Technology; and Marri Laxman Reddy Institute Of Technology And Management on September 07, 2026, for Fpga Accelerator For High-Speed Computational Single Mac Architecture.
Inventors include Mr. S. Naveen Kumar; Mr. G. Akhil; Mr. G. Nikhil Sai; and Mr. Ch. Sai Harshith.
The application for the patent was published on September 11, 2026, under issue no. 37/2026.
Abstract: The present invention relates to an FPGA accelerator for high-speed computational Single Multiply–Accumulate (MAC) architecture employing a pipelined design for improved computational efficiency and throughput. The invention divides the MAC operation into multiple stages, including input registration, multiplication, and accumulation stages separated by pipeline registers. The pipelined structure reduces critical path delay and enables operation at higher clock frequencies compared to conventional architectures. The multiplication operation is implemented using FPGA DSP blocks to achieve efficient arithmetic computation and optimized hardware utilization. The proposed architecture supports continuous streaming data processing and produces one output per clock cycle after pipeline initialization. The invention further incorporates synchronized control logic for stable data propagation and reliable operation. The architecture is scalable, modular, and suitable for digital signal processing, embedded systems, communication systems, neural network acceleration, and real-time computational applications. The invention provides improved throughput, reduced delay, efficient FPGA resource utilization, and enhanced computational performance suitable for modern high-speed digital processing systems.
Disclaimer: Curated by HT Syndication.
