MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202441104639 A) filed by Samsung Electronics Co. , Ltd.; and Indian Institute Of Science, Bangalore on December 30, 2024, for Electrostatic Discharge Protection Circuit With Lower Trigger Voltage And Reduced Input/Output Capacitance.
Inventors include Goyal, Mitesh; Chaturvedi, Mukesh; Vaidya, Mahesh; and Shrivastava, Mayank.
The application for the patent was published on July 03, 2026, under issue no. 27/2026.
Abstract: There is provided an Electrostatic Discharge (ESD) protection circuit including a Silicon Controlled Rectifier (SCR). The SCR includes an N+ diffusion region (Npick terminal), formed in an n-well (NW) region, and connected to a source terminal of a P-channel Metal Oxide Semiconductor (PMOS) transistor of an inverter, and a P+ diffusion region (Ptrig terminal), formed in a p-type substrate, and connected to a source terminal of an N-channel Metal Oxide Semiconductor (NMOS) transistor of the inverter.
Disclaimer: Curated by HT Syndication.
