MUMBAI, India, Sept. 14 -- Intellectual Property India has published a patent application (202641107161 A) filed by Hindustan Institute Of Technology And Science on September 07, 2026, for Efficient Embedding Of Complete Bipartite Graphs Into Line Graphs Of A Complete K-Ary Tree And Its Application In Vlsi Layout.
Inventors include N. Jothilakshmi; R. Sundara Rajan; and D. Ahima Emilet.
The application for the patent was published on September 11, 2026, under issue no. 37/2026.
Abstract: Disclosed herein is an innovative method for embedding complete bipartite graphs into the line graphs of a complete k-ary tree for applications in VLSI and integrated circuit design. The proposed technique provides an effective framework for minimizing wirelength and optimizing communication layouts, thereby improving the performance of interconnection networks. By employing a structured embedding strategy and exploiting the hierarchical organization of the line graphs of a complete k- ary tree of level l, the method facilitates efficient placement of vertices and communication paths within the host network. The resulting layout exhibits reduced wirelength, balanced utilization of communication resources, and lower routing congestion, leading to enhanced communication efficiency and system reliability. Furthermore, the recursive structure of the host graph enables scalable implementations suitable for large and complex circuit architectures. The mapping and labeling scheme adopted in the embedding process simplifies implementation while preserving the structural properties of both the guest and host networks. This invention offers a practical and efficient solution for VLSI layout optimization through the embedding of complete bipartite graphs into the line graphs of a complete k-ary tree of level l, yielding significant improvements in signal transmission, interconnection efficiency, power consumption, and overall system performance.
Disclaimer: Curated by HT Syndication.
