MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202617069658 A) filed by International Business Machines on June 03, 2026, for Dual Side Cut Staggered Stacked Field Effect Transistor.
Inventors include Xie, Ruilong; Zhang, Chen; Wang, Junli; and Choi, Kisik.
The application for the patent was published on July 03, 2026, under issue no. 27/2026.
Abstract: According to the embodiment of the present invention, a semiconductor device includes a plurality of nanodevices (ND1, ND2) including a plurality of upper transistors and a plurality of lower transistors. The plurality of nanodevices include an upper active region (135, 140, 145) and a lower active region (120, 125) that are offset from each other across the plurality of upper transistors and the plurality of lower transistors. A first frontside gate cut dielectric pillar (190, 195) is located adjacent to and parallel to a first nanodevice of the plurality of nanodevices along an x-axis. A backside surface of the first frontside gate cut dielectric pillar extends a first width along a y- axis. A first backside dielectric fill (240, 245) is in direct contact with the backside surface of the first frontside gate cut dielectric pillar. A frontside surface of the first backside dielectric fill extends a second width along the y-axis. The second width is greater than the first width.
Disclaimer: Curated by HT Syndication.
