MUMBAI, India, Aug. 31 -- Intellectual Property India has published a patent application (202641099764 A) filed by Amrita Vishwa Vidyapeetham on August 18, 2026, for Dual-Channel Memory Control Device For Synchronizing Independent Memory Channels And Generating A Unified Data Output.
Inventors include Siddireddy, Kapileswarreddy; and Hegde, Ganapathi.
The application for the patent was published on August 28, 2026, under issue no. 35/2026.
Abstract: The present disclosure relates to a dual-channel memory control device (100) including a first memory interface (102) connected to a first memory channel (104), and a second memory interface (106) connected to a second memory channel (108). A command scheduler (110) independently schedules memory transactions for the first memory channel and the second memory channel, while the finite state machine controls read, write, row activation, burst transfer, precharge, and refresh operations. A synchronization circuit (112) aligns data received from both memory channels, and the data aggregation circuit combines 2 synchronized 32-bit data streams into a unified 64-bit output data stream independently of an input data sequence. The memory control device (100) supports DDR3, DDR4, DDR5, and DDR6 SDRAM, including data rates up to 8400 MT/s, and achieves approximately 35% lower logic utilization and approximately 18% lower power consumption while providing scalable multi-channel memory operation, reliable data transfer, increased throughput, and reduced latency.
Disclaimer: Curated by HT Syndication.
