MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202641110675 A) filed by National Institute Of Technology Karnataka on September 15, 2026, for Direction-Aware Selective Vertical Routing For Port-Constrained 3d Network-On-Chip Architecture.
Inventors include Rathnamala Rao; and M. N. Saranya.
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: ABSTRACT DIRECTION-AWARE SELECTIVE VERTICAL ROUTING FOR PORT-CONSTRAINED 3D NETWORK-ON-CHIP ARCHITECTURE The present invention relates to direction-aware selective vertical routing system and method, for a port-constrained three-dimensional (3D) Network-on-Chip (NoC) architecture. The system comprises five-port planar routers arranged in a two-dimensional mesh across a plurality of stacked layers, wherein predetermined unused planar ports of selected boundary routers are reassigned to establish vertical inter-layer communication without introducing dedicated UP and DOWN ports, thereby preserving the original five-port router architecture and router radix. The disclosed routing method determines whether packet transmission requires intra-layer or inter-layer communication. For intra-layer communication, deterministic XY routing is performed. For inter-layer communication, the routing method determines the required vertical direction, identifies routers capable of supporting the required vertical traversal, and forwards packets through predetermined gateway routers when direct vertical traversal is unavailable.
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