MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641075080 A) filed by Vardhaman College Of Engineering on June 17, 2026, for Design Techniques For Controlling Leakage In Sub-Threshold Vlsi Systems.
Inventors include I. Babu; M. Geetanjali; D. Gurunath; Tareeq Zaid; Sangeeta Singh; G. Akshaya; Kura Karthik; Palli Vishwa Teja; and Dareddy Karthik Reddy.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: Design Techniques for Controlling Leakage in Sub-Threshold VLSI Systems is the proposed invention. The invention disclosed here proposes a unique leakage control technique using Adaptive Body Biasing (ABB) combined with Fully Depleted Silicon-On-Insulator (FD-SOI) technology. The proposed method dynamically adjusts the threshold voltage of the transistors by forward or reverse body bias depending on the real-time operating parameters such as workload, temperature and supply variations. The system also has a monitoring and control mechanism that monitors circuit activity continuously and adjusts the body bias to achieve the best possible trade-off between performance and power consumption. The forward body bias increases the speed in active mode, while reverse body bias suppress the leakage currents in idle mode. Using FD-SOI technology instead of traditional CMOS designs, a larger biasing range and better electrostatic control can be achieved, which leads to more efficient leakage reduction and less variability.
Disclaimer: Curated by HT Syndication.
