MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202641075333 A) filed by Hindusthan Institute Of Technology on June 18, 2026, for Design Of Approximate Multiplier Based On Operand Partitioning.
Inventors include Dr. C. Natarajan; Dr. S. Kavitha; Dr. B. Paulchamy; Dr. J. Manikandan; Mr. M. Ashwin Bharathi; K. R. Kannan; Dr. S. Jeyabharathi; and Dr. P. Jayachitra.
The application for the patent was published on July 03, 2026, under issue no. 27/2026.
Abstract: Approximate multipliers are widely used in error-tolerant applications, where a slight loss in accuracy is acceptable in exchange for reduced -power consumption and delay. In a Static Segmented Multiplier (SSM) the operands are statically split into two m-bit segments. This approach greatly simplifies hardware implementation, reducing power consumption, since leadingone detectors and shifters are not required. On the other hand, for the same inner m x m multiplier, static segmentation results in larger errors compared to dynamic segmentation. A hybrid approach is proposed in, using a first static segmentation stage and an inner multiplier employing dynamic segmentation. In this paper we perform a detailed analysis of SSMs and we propose some improvements to the basic architecture. In this work, an approximate multiplier based on fixed partitioning is proposed. In the proposed design, a set of m contiguous bits (a segment) is extracted from each n-bit operand, and the two m-bit segments are multiplied using a small internal m x m multiplier. The resulting partial product is appropriately shifted to obtain the final result To further enhance accuracy, a simple yet ef~ective correction technique is introduced, which significantly reduces the approximation error while maintaining low hardware overhead. To minimize design complexity, the partial product of the partitioned multiplier is divided into Most Significant Part (MSP) and Least Significant Part (LSP), with an inner approximation applied to the LSP portion. Comparative analysis demonstrates that the proposed static multiplier with correction achieves favorable trade-offs in power-area-delay versus error metrics. The inner approximation approach results in reduced power consumption and area compared to existing designs. Owing to these characteristics, the proposed multiplier is a promising candidate for applications that can tolerate limited computational errors. The proposed multiplier is designed using Verilog HDL and simulated. using Modelsim software. The designed is synthesized and parameter analysis performed using Xilinx ISE.
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