MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641115485 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi Institute Of Engineering And Technology on September 26, 2026, for Design Of A Reversible Vedic Multiplier Using Brent-Kung Adder For High-Speed And Low-Power Arithmetic Applications.
Inventor includes Dr. V Pradeep Kumar.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT [0027] Reversibility means that a system or process has the mastery to go back to an original condition by being shadowed each output to a unique input. Let’s hash it out about digital circuits, and this reveals that is that every output state is tied to a certain input state. By adopting this strategy, we ensure we avoid losing of any information, and the process can be reversed fruitfully. We use reversible logic gates in digital circuits for the aim of reversibility.Adders have important tasks in digital systems. Because of their fast carry propagation, the parallel prefix adders are fast as compared with the conventional adders. In this paper, a pioneering design and implementation of a Brent Kung adder is presented followed by the implementation of a Vedic multiplier using reversible logic gates such as PERES, UPG and BME. The proposed approach is shown to achieve enhanced efficiency and performance metrics by effectively integrating these gates. The most notable aspect of this design is somehow obtaining reversibility with a small number of gates and ancilla inputs but with efficient garbage output management. The Xilinx Vivado version 2023.2 software was used, and the simulation and design were done. We design the architecture of a 4-bit,8-bit Brent-Kung adder with minimal quantum cost and gates. These adders are utilized to design a 4-bit,8-bit Vedic multiplier and were implemented in the FPGA board. As these multipliers are made using parallel prefix adders, they can lead to usage in multiple applications like ALUs, Quantum computing, DSP applications, FPGA and ASIC designs, etc.
Disclaimer: Curated by HT Syndication.
