MUMBAI, India, Sept. 14 -- Intellectual Property India has published a patent application (202641107223 A) filed by Mlr Institute Of Technology; and Marri Laxman Reddy Institute Of Technology And Management on September 07, 2026, for Design Of 32-Bit Arithmetic Logic Unit.
Inventors include Dr. K. Nishanth Rao; Mr. M. Raju Nayak; Ms. Chigurupally Rithika; and Mr. Kallem Ram Charan.
The application for the patent was published on September 11, 2026, under issue no. 37/2026.
Abstract: The present invention discloses a low-power, high-speed 32-bit Arithmetic Logic Unit (ALU) using 90 nm CMOS technology for applications in digital and embedded systems. The ALU performs arithmetic operations such as addition and subtraction and logical operations, including AND, OR, XOR, NAND, and NOT, through a modular, hierarchical design based on cascaded 1-bit cells forming higher-order modules. Each cell integrates arithmetic and logic circuits, multiplexers, control inputs, and carry/borrow propagation paths, enabling efficient multi-bit processing. Simulation results confirm correct functionality with a propagation delay of about 110.53 picoseconds and power consumption of approximately 1.15634 milliwatts, making the design suitable for high-speed, low-power applications.
Disclaimer: Curated by HT Syndication.
