MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641114488 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi on September 24, 2026, for Design And Verilog Implementation Of An Optimized Risc Alu With Parallel Prefix Addition And Booth Multiplication.
Inventor includes Dr. K Lv Ramana Kumari.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT [0021] The performance and efficiency of modern digital systems heavily depend on the design of core arithmetic units such as the Arithmetic Logic Unit (ALU), adder, and multiplier. In this project, we propose the design and verilog implementation of a high-performance ALU for Reduced Instruction Set Computing (RISC) architecture, which integrates two optimized arithmetic components: the Kogge-Stone Adder and the Booth Multiplier. RISC processors are known for their simplified instruction set, allowing for faster execution rates, and hence demand arithmetic units that are both fast and resource-efficient. [0022] The Kogge-Stone Adder, a parallel prefix adder, is chosen due to its logarithmic delay characteristics and ability to support high-speed addition operations, essential for time-critical applications. It is preferred over traditional adders like Ripple Carry or Carry-Lookahead due to its superior performance in large-bit operations. In parallel, Booth’s multiplication algorithm is implemented for its efficiency in signed number operations. By encoding the multiplier bits, Booth’s algorithm reduces the number of partial products, which decreases the computation time and conserves hardware resources. The RISC ALU is designed to support a wide range of arithmetic and logical operations including addition, subtraction, AND, OR, XOR, and multiplication. All components are modeled using Verilog and synthesized using the Xilinx Vivado design suite. Functional verification is carried out through simulation.
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