MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641114784 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi Institute Of Engineering And Technology on September 24, 2026, for Design And Performance Optimization Of A 12 Nm Gaafet-Based Dynamic Comparator For High-Speed Low-Power Applications.
Inventor includes Dr. E. Vijaya Babu.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT [0020] With the quick development of analog and mixed-signal circuits, there is a growing need for high-speed, low-power comparators, especially for memory sensing and analog-to-digital converters (ADCs). The design and performance assessment of a dynamic comparator utilizing Gate-All-Around Field-Effect Transistor (GAAFET) technology at the 12nm node are the main objectives of this project. HSPICE is used to implement and simulate the designed comparator, while Cosmos Scope is used to analyze the waveform. We evaluate the GAAFET-based comparator's efficiency by contrasting its power consumption and latency with FinFET and traditional CMOS solutions. The findings show that because of its better electrostatic control and fewer short-channel effects, GAAFET technology dramatically lowers power dissipation while achieving increased speed. Comparative analysis reveals that GAAFET-based designs outperform FinFET and CMOS counterparts, making them a promising choice for next-generation low-power, high-speed applications. The findings of this study highlight the potential of GAAFETs in high-performance analog circuit design, providing insights into their advantages over existing semiconductor technologies.
Disclaimer: Curated by HT Syndication.
