MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641115431 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi Institute Of Engineering And Technology on September 26, 2026, for Design And Optimization Of An 8-Bit Reversible Vedic Multiplier Using Kogge-Stone Adder For Low-Power Computing.
Inventor includes Dr. N Neelima.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT [0025] Reversible logic has garnered significant attention in emerging fields such as quantum computing, low-power VLSI design, and nanotechnology due to its ability to reduce energy dissipation. Multipliers are fundamental components in digital systems, particularly in high-speed and low-power applications. This research work proposes a novel design of an 8-bit Vedic multiplier using reversible logic techniques. The architecture integrates the efficiency of Vedic multiplication with the advantages of reversible logic gates to achieve an optimized design. A reversible 8-bit Kogge-Stone adder is utilized in the final addition stage to enhance the speed and efficiency of the proposed multiplier architecture. Key parameters such as gate count, garbage outputs, ancilla inputs, and quantum cost are analyzed and minimized. The implementation utilizes the Urdhva Tiryakbhyam sutra of Vedic mathematics, known for its parallel computation approach. Reversible gates such as Peres, Feynman, and BRG are employed to construct the multiplier with minimal logical overhead. Simulation and analysis have been carried out to verify the functionality and efficiency of the proposed design. The results demonstrate a significant reduction in garbage outputs and power consumption, affirming the design’s suitability for quantum and optical computing applications, making it a promising solution for next-generation low-power arithmetic circuits.
Disclaimer: Curated by HT Syndication.
