MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641114486 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi Institute Of Engineering And Technology on September 24, 2026, for Design And Fpga Implementation Of A Resource-Efficient Ahb-Apb Bridge For Soc Applications.
Inventor includes Dr. V. Sagar Reddy.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT [0021] Integrating high-speed processing elements and low-speed peripheral devices forms part of key design challenges in modern system-on-chips (SoCs). Effective communication between these two domains is a prerequisite to achieving sustained high performance at the system level. For instance, an AHB bridge would perform the function of allowing access by peripherals connected through the advanced peripheral bus (APB) to the higher bandwidth AHB. In effect, the AMBA defines two types of buses for different categories of traffic transfer: AHB for high-throughput data transfer and APB for power-efficient communication with peripheral devices. An AHB-APB bridge is fundamental to establishing a way to facilitate seamless data exchange between the two buses. Therefore, this paper provides a comprehensive design of such a bridge, detailing how it converts the complex multi-pipeline AHB transactions into simple, sequential APB transactions. In terms of timing mismatches and protocol translations, the bridge performs well without compromising speeds or data integrity. [0022] The evaluated bridge works fine and is able to produce functional correctness and timing compliance in different scenarios across the full test cases in a SystemVerilog-based simulation environment. The reliable and performing simulation results are captured through their synthesis on an FPGA platform. Hardware synthesis reports demonstrate that the design makes efficient use of minimal FPGA resources as well as minimal delay, which makes itself highly appropriate for applications of the real time. This infers that the AHB- APB bridge is not only equipped for modern SoC architectures but also optimally tailored to embedded systems that require low latency and low power consumption. All in all, it becomes a proven, scalable way to bridge high-speed processing with peripherals for varied application markets.
Disclaimer: Curated by HT Syndication.
