MUMBAI, India, Aug. 31 -- Intellectual Property India has published a patent application (202621070613 A) filed by Indian Institute Of Technology Indore on June 05, 2026, for Dbim-Cim: Dynamic Bitline Computation-In-Memory Using Selective-Bypass Mac.
Inventors include Vikash Vishwakarma; Pratham Sharma; and Santosh Kumar Vishvakarma.
The application for the patent was published on August 28, 2026, under issue no. 35/2026.
Abstract: ABSTRACT DBIM-CIM: DYNAMIC BITLINE COMPUTATION-IN-MEMORY USING SELECTIVE-BYPASS MAC The invention relates to compute-in-memory systems for neural-network inference, and particularly to a DRAM subarray compute fabric that reduces inference-time recomputation and switching activity. Stored weight rows support column-parallel operation, while a weight write or update path and a Weight-Change Flag latch detect weight modification events. In response, a Bitline-Adjacent Weight Pre-Sum unit simultaneously activates adjacent stored weight rows to generate an intermediate combined value through intrinsic bitline interaction, and a Pre-Sum Latch retains the value for persistent reuse until a subsequent weight update occurs. A Selective Computation Unit receives stored values, the retained intermediate combined value, and an activation input, and selectively outputs zero, an individual stored value, or the retained combined value, including zero-activation bypass. Outputs from multiple Selective Computation Units are reduced by a Carry-Save Adder tree, and a Precision Output Stage supports INT4, INT8, and INT16 modes with sign extension to produce a mac_result.
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