MUMBAI, India, Aug. 17 -- Intellectual Property India has published a patent application (202647094825 A) filed by Qualcomm Incorporated on August 05, 2026, for Compressing Data Portions In A Translation Lookaside Buffer.
Inventors include Montero, Adrian; Nair, Roshan Sreekumar; and Sinha, Vikas Kumar.
The application for the patent was published on August 14, 2026, under issue no. 33/2026.
Abstract: Certain aspects of the present disclosure provide techniques and apparatus for translation lookaside buffer (TLB) compression. Embodiments include determining that a plurality of physical memory addresses, associated with a plurality of virtual memory addresses, are contiguous with one another and share one or more common address bits or one or more common attribute bits, wherein each respective physical memory address of the plurality of physical memory addresses corresponds to a separate respective physical memory page. Embodiments include generating a tag for an entry in a TLB, the tag representing the plurality of virtual memory addresses. Embodiments include associating, in the entry in the TLB, the tag with data comprising: a single instance of the one or more common address bits or the one or more common attribute bits of the plurality of physical memory addresses; and other bits of the plurality of physical memory addresses.
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