MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641075083 A) filed by Vardhaman College Of Engineering on June 17, 2026, for Compact And Energy-Aware Vlsi Design For Real-Time Deep Learning Applications.
Inventors include S. Rajendar; M. Nagarjuna; C. Padmini; R. Phani Vidyadhar; Sushanta Debnath; P. Harshitha; L. Madhurya; Ganja Datta Sai Naga Venkat Vinay; and Mustigolla Rishith Yadav.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: Compact and Energy-Aware VLSI Design for Real-Time Deep Learning Applications is the proposed invention. The proposed invention is aimed at combining optimised parallel processing units with a minimised hardware footprint to achieve high computational performance while reducing the silicon area. To overcome the energy constraints, the design follows adaptive power management techniques such as clock gating, power gating and dynamic voltage and frequency scaling. The system adapts its operation to the workload requirements. The data transfers that consume power are kept to a minimum by efficient memory management such as on- chip buffering and data reutilization. The architecture also enables low-precision computation to further reduce energy consumption without major impact on accuracy. The proposed VLSI system is more efficient in performance by integrating compact design concepts, intelligent energy optimisation and high throughput processing. Therefore, it is suitable for real-time resource constrained deep learning applications.
Disclaimer: Curated by HT Syndication.
