MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202641085538 A) filed by Dr. Sanju V on July 13, 2026, for Av-Ricobit (adaptive Variable - Ring Connected Binary Tree): A Topology With Variable Packet Size - Topology For Future Generation Multi Core High Performance Processor.
Inventors include Dr. Sanju V; and Dr. Meenakshi Sundaram A.
The application for the patent was published on August 07, 2026, under issue no. 32/2026.
Abstract: Network-on-Chip (NoC) is an approach in which a network-based communication mechanism is used to interconnect various modules within a chip. In this paradigm, data is transmitted in the form of packets between processing elements. Common topologies employed for such interconnections include mesh, torus, and RiCoBiT (Ring Connected Binary Tree), Among these, RiCoBiT demonstrates superior performance compared to mesh and torus topologies, primarily due to its lower maximum hop count and reduced average hop count—both of which are critical factors influencing communication efficiency. However, the original RiCoBiT topology lacked an adaptive routing mechanism, which led to the development of A-RiCoBiT (Adaptive Ring Connected Binary Tree), This enhanced version introduced adaptability in routing, improving overall flexibility. Despite this advancement, A-RiCoBiT suffers from increased packet transmission time. This is mainly due to the use of fixed, relatively large packet sizes, which results in inefficiencies when transmitting smaller amounts of data. To address this limitation, the proposed AV-RiCoBiT topology introduces variable-sized packets. By allowing packet sizes to be adjusted according to the data being transmitted, smaller packets can be sent more quickly, thereby improving transmission speed and enhancing overall system performance.
Disclaimer: Curated by HT Syndication.
