MUMBAI, India, Nov. 2 -- Intellectual Property India has published a patent application (202647127867 A) filed by Boe Technology Group Co. , Ltd. on October 27, 2026, for Array Substrate And Display Panel.
Inventors include Ning, Ce; Liu, Fengjuan; Wang, Lizhong; Zhao, Ce; and Yuan, Guangcai.
The application for the patent was published on October 30, 2026, under issue no. 44/2026.
Abstract: An array substrate, comprising a first base substrate (10), and a first conductive layer (20), a buffer layer (BUF), a semiconductor layer (30), a gate insulating layer (GI), and a second conductive layer (40) sequentially arranged in a direction away from the first base substrate (10). The first conductive layer (20) comprises a plurality of data signal lines (DL), and the plurality of data signal lines (DL) are distributed at intervals along a first direction and extend along a second direction as a whole. The semiconductor layer (30) is located on the side of the buffer layer distant from the first base substrate (10) and comprises a first semiconductor pattern (31). The second conductive layer (40) is located on the side of the gate insulating layer (GI) distant from the first base substrate (10), and comprises a first source (S1), a first drain (D1), and a first gate (G1). The array substrate comprises a first via hole (V1), and the first via hole (V1) runs through the gate insulating layer (GI) and the buffer layer (BUF) and exposes at least part of the data signal line (DL). The array substrate comprises a plurality of first transistors (T1) located in a display area; each first transistor (T1) comprises the first semiconductor pattern (31), the first gate (G1), the first source (S1), and the first drain (D1); and the first source (S1) passes through the first via hole (V1) to be electrically connected to the data signal line (DL).
Disclaimer: Curated by HT Syndication.
