MUMBAI, India, Aug. 31 -- Intellectual Property India has published a patent application (202647099811 A) filed by Boe Technology Group Co. , Ltd.; and Chengdu Boe Display Sci-Tech Co. on August 18, 2026, for Array Substrate, Display Panel, And Display Device.
Inventors include Xiao, Feng Pctcn No; Zhu, Wei; Yang, Guidong; Qi, Xiaojing Wo No; Guan, Yue; and Deng, Yu Application Number.
The application for the patent was published on August 28, 2026, under issue no. 35/2026.
Abstract: An array substrate (001), a display panel (PNL), and a display device. The array substrate (001) comprises: a base substrate (101); a plurality of pixel electrodes (102) arranged in an array on the base substrate (101); a plurality of data lines (103) extending in column gaps between the pixel electrodes (102); a plurality of gate lines (104) extending in row gaps between the pixel electrode (102), two gate lines being included in the same row gap (104); a plurality of first common electrode lines (105) arranged in the same layer as the plurality of gate lines (104), each first common electrode line (105) being located between the two gate lines (104) in the same row gap; a plurality of second common electrode lines (106) arranged in the same layer as the plurality of data lines (103), the second common electrode lines (106) and the data lines (103) being alternately arranged in different column gaps between the pixel electrodes (102), and the orthographic projections of the second common electrode lines (106) on the base substrate (101) and the orthographic projections of the first common electrode lines (105) on the base substrate (101) intersecting with one another to form a mesh; an insulating layer (107) comprising first via holes (V1) exposing the positions at which the first common electrode lines (105) intersect with the second common electrode lines (106); and transparent electrodes (108) respectively electrically connected to the first common electrode lines (105) and the second common electrode lines (106) by means of the first via holes (V1).
Disclaimer: Curated by HT Syndication.
