MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202641111839 A) filed by Vellore Institute Of Technology, Chennai on September 17, 2026, for Arithmetic Processing System And Method For Performing Rounding-Error-Compensated Digital Arithmetic.
Inventors include Sathyavathi N. S; and Augusta Sophy Beulet P..
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: An arithmetic processing system (100) and method (400) for performing rounding-error-compensated digital arithmetic. System includes arithmetic unit that perform arithmetic operation on input operand to produce arithmetic result having bits beyond target precision. Bit identification unit identify, from arithmetic result, set of bits that collectively characterize discarded portion of arithmetic result relative to target precision, including boundary bit, first discarded bit, second discarded bit, and composite bit derived from logical combination of all remaining bits beyond second discarded bit. Error determination unit determine rounding error value corresponding to identified set of bits and selected rounding method using stored mapping between combinations of set of bits and corresponding rounding error values for rounding methods. Rounding unit apply selected rounding method to produce rounded arithmetic result. Correction unit generate corrected arithmetic result based on determined rounding error value and rounded arithmetic result to produce arithmetic output having reduced rounding error.
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