MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202647111705 A) filed by Google LLC on September 17, 2026, for Area-Efficient Asymmetric Multiply-And-Accumulate Unit Design For Various Hybrid Quantization Support.
Inventors include Yoon, Hongil; Kane, Anand Suresh; Cho, Benjamin Youngjae; Hwang, Inho; and Desrosiers, David Paul Wunsch.
The application for the patent was published on September 25, 2026, under issue no. 39/2026.
Abstract: Methods and systems are described for performing multiply accumulate operations on input data with multiple bit widths. A multiply accumulate device that includes a first multiply unit having a first bit width and a second multiply unit having a second bit width that is smaller than the first bit width. The device is reconfigurable to perform a first multiplication operation using the first multiply unit when input data comprises input operands having the first bit width and a plurality of second multiplication operations using the first multiply unit and the second multiply unit when input data comprises input operands having the second bit width.
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