MUMBAI, India, Aug. 10 -- Intellectual Property India has published a patent application (202611074754 A) filed by Geetika Srivastava on June 16, 2026, for Approximate Computing Mac Unit Using Mabf Encoding And Cross-Term Residual Tracking For Edge Inferences.

Inventors include Geetika Srivastava; Aditya Kumar Sharma; Mohammad Ariz; Sandeep Kumar Pandey; and Raghvendra Tiwari.

The application for the patent was published on July 31, 2026, under issue no. 31/2026.

Abstract: A pipelined multiply-accumulate (MAC) unit is disclosed for neural network inference on resource-constrained field-programmable gate array (FPGA) platforms. The unit replaces conventional parallel multipliers with approximation logarithmic arithmetic, reducing silicon area and dynamic power consumption while maintaining acceptable numerical accuracy. Each signed 8-bit integer operand is encoded into a compact 8-bit Modified Adaptive Block Floating-Point (MABF) codeword comprising a sign bit, a 3-bit exponent, a 3-bit mantissa, and a combined zero/gating flag. The encoded operands flow through a nine-stage pipeline (S0–S8) that performs log-domain multiplication via addition, dual-operand k-correction using a 16-entry lookup table, and antilogarithmic conversion. Two auxiliary mechanisms support the core datapath. Adaptive Significance Gating (ASG) suppresses operands whose exponent falls below a layer-dependent threshold stored in a 16-entry, 2-bit lookup table, reducing unnecessary switching activity. Cross-Term Residual Tracking (CTRT) monitors the mantissa cross-product residual and exports a correction flag and a 6-bit saturating error accumulator as metadata, without modifying the computed product. Products accumulate in a 24-bit signed linear accumulator with 8-bit clamped output and overflow detection. All these mechanisms operate at 100 MHz with an initiation interval of one cycle and a latency of eight cycles, sustaining 100 million MAC operations per second. Post-route implementation on the Xilinx Zynq-7000 (xc7z020clg484-1) consumes 267 Slice LUTs, 309 Slice Registers, and zero Block RAM. Total on-chip power is 126 mW, of which only 23 mW is dynamic.

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