MUMBAI, India, July 30 -- Intellectual Property India has published a patent application (202641088888 A) filed by Vit-Ap University on July 21, 2026, for Apparatus For Timing Synchronization In Visible Light Communication Receivers.
Inventors include Suseela Vappangi; Sudha Ellison Mathe; and Purnachand Nalluri.
The application for the patent was published on July 24, 2026, under issue no. 30/2026.
Abstract: An apparatus (100) for timing synchronization in a visible light communication may include a sample buffer (102) to receive and store digitized samples representative of a received optical communication signal. A first timing estimation engine (104) may process the digitized samples based on a periodicity characteristic to generate a first symbol-timing-offset estimate, while a second timing estimation engine (106) may process the digitized samples based on a predetermined training-symbol characteristic to generate a second symbol-timing-offset estimate. Respective confidence calculators (108A, 108B) may generate first and second confidence information associated with the corresponding symbol-timing-offset estimates. A confidence-fusion and arbitration engine (110) may combine the first and second symbol-timing-offset estimates based on the respective confidence information to generate a unified symbol-timing-offset estimate. A window-alignment engine (112) may determine a symbol-processing window based on the unified symbol-timing-offset estimate and generate timing-alignment information for processing the received optical communication signal.
Disclaimer: Curated by HT Syndication.
