MUMBAI, India, June 26 -- Intellectual Property India has published a patent application (202621051273 A) filed by Sage University on April 22, 2026, for Apparatus For Tamper-Resistant Pos Transaction Processing With Impedance-Based Hardware Self- Authentication.
Inventors include Dr. Prashant Jain; Ms. Sakshi Agrawal; Prof. Kundan Kumar Mishra; Prof. Sheshansh Barmaiya; Sumit Gupta; and Manas Rathore.
The application for the patent was published on June 19, 2026, under issue no. 25/2026.
Abstract: ABSTRACT The present disclosure relates to tamper-resistant point-of-sale transaction processing. The apparatus (100) includes a printed circuit board (102) having designated test traces (104) routed through security-critical zones, and a microcontroller (106) operatively coupled to the printed circuit board (102). The microcontroller (106) receives impedance data from the test traces (104) and capacitance data from electrodes disposed around a card reader bezel (122) and keypad surround (124). Impedance data is compared against a factory-enrolled baseline to generate a hardware integrity anomaly signal, while capacitance data is compared against a stored baseline to generate an overlay detection signal. The microcontroller (106) further correlates sensor data from a multi-sensor physical intrusion array (108) to generate a tamper signal, commanding erasure of all cryptographic keys and transmission of a tamper alert message to a remote monitoring server (118). This provides comprehensive, multi-layered hardware authentication and intrusion detection for secure payment terminals. FIG. 1
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