MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202641078563 A) filed by Sr University on June 25, 2026, for An Integrated Power-Reduction Framework For Bcd Arithmetic Units Using Multi-Vdd, Clock Gating, And Power Gating.
Inventors include Dr. Ts. Narayanamurthy; Dr. Ch. Rajendra Prasad; and Dr. Roseline Oluwaseun Ogundokun.
The application for the patent was published on July 03, 2026, under issue no. 27/2026.
Abstract: AN INTEGRATED POWER-REDUCTION FRAMEWORK FOR BCD ARITHMETIC UNITS USING MULTI-VDD, CLOCK GATING, AND POWER GATING The present invention relates to an integrated power-reduction framework for BCD arithmetic units and VLSI integrated circuits using coordinated multi-VDD, clock gating, and power gating techniques under adaptive centralized control. The framework continuously monitors switching activity, idle duration, utilization, and performance parameters of functional units to determine real-time workload conditions. Based on the monitored activity, adaptive control logic dynamically manages clock distribution, voltage assignment, and power gating operations. Clock gating reduces unnecessary switching activity in idle circuits, multi-VDD control assigns appropriate voltage levels according to performance requirements, and power gating disconnects inactive blocks to minimize leakage power. The integrated coordination of these techniques enables substantial reductions in dynamic and static power consumption while maintaining functional correctness, timing performance, reliability, and scalability. The framework is particularly suitable for low-power BCD arithmetic units and modern VLSI systems operating under varying workload conditions.
Disclaimer: Curated by HT Syndication.
