MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641115482 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi Institute Of Engineering And Technology on September 26, 2026, for An Energy-Efficient Tigfet-Based Sram Cell Architecture Supporting Binary And Ternary Logic For High-Density Memory Applications.
Inventor includes Dr. S Rajendra Prasad.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: ABSTRACT [0030] Static Random-Access Memory (SRAM) cells are indispensable components in modern integrated circuits, playing a crucial role in applications requiring high speed data access and low power consumption. However, with the continued scaling of semiconductor technology, traditional CMOS- based SRAM cells are increasingly challenged by issues such as higher power consumption. Thus new technologies have evolved presenting an alternative to the existing CMOS technology with significant advantages over it. This paper presents the design of 6T SRAM cell, Schmitt trigger based 12T SRAM (ST12T) SRAM cell, Half-Select Free Write Assist 9T (HFWA9T) SRAM cell and 11T SRAM cell in TIGFET technology and implemented using ternary logic. The designs have been evaluated using Synopsys HSPICE 2019 and the values of static power, dynamic power, read delay, write delay have been computed. The results show that the TIGFET SRAM cells offer significantly lower power consumption while maintaining comparative performance in terms of read and write delays. SRAM cells in binary and ternary logic show similar power consumption, indicating ternary logic offers higher data density without a major power increase.
Disclaimer: Curated by HT Syndication.
